FOR IMMEDIATE RELEASE
Aldec Extends Powerful HDL Simulation to Linux Platforms
Riviera™ is the first product to offer integrated HDL design entry, simulation and debugging on the Linux Platform
Henderson Nevada, November 13th, 2000 -- Aldec, Inc., a leading supplier of HDL design entry and verification software for programmable logic devices, announced today, Riviera, a new Linux-based mixed HDL design environment. The Riviera product family is based on Aldec’s core HDL simulation technology and is focused on providing the highest performance ASIC and high-density FPGA simulation products. Riviera is the industry’s first integrated design verification environment for Linux operating systems that includes an HDL Editor, debugger and VHDL, Verilog and EDIF simulation from one product family. Riviera for Linux is the first in a series of advanced simulation products that will also include future support for both NT and UNIX platforms.
Meeting User Needs
Feedback from current Windows based customers and the requests from HDL simulation customers looking to take advantage of the PC’s processing capabilities, has propelled Aldec into supporting the Linux operating system. As the number of high density FPGA design starts grow, users are requiring PC based HDL simulation products that can process extensive regression tests without limitations from their operating system. Riviera is focused on providing a comprehensive set of stand-alone applications that can be run as separate point tools or as a completely integrated design environment on Linux. Aldec’s internal SQA team has proven that running Riviera in batch mode on Linux for regression testing is up to 5x faster then on Windows NT.
As the industry realizes that the performance of Linux equals that of UNIX platforms and that the operating system is stable, there will be a major shift to Linux based server farm verification because of the significant advantages in almost every area: memory operations, file handling and batch processing.
What’s Included
Riviera includes several stand-alone applications that support VHDL, Verilog and EDIF mixed simulation from a common kernel, HDL Editor, Graphical Waveform Viewer and library management tools. The product features source code debugging, breakpoint setting, compile all with file reorder and the ability to single step through the simulation data to display detailed information on VHDL and Verilog components and their relationships.
Benefits of Riviera Simulator
Riviera can be easily integrated with existing design entry systems and 3rd party EDA software products through Tcl/Tk, PERL and PLI interfaces.
- Allows users to share libraries for team based design and create sub-designs using these global libraries
- Ideal for server based installations to allow multi-user access
- Fast expandable scripting engine and low memory consumption
- Supports Aldec’s integrated Hardware Embedded Simulation (HESTM) technology for hardware acceleration and Incremental Prototyping™
“The Riviera product line is aimed at supporting the ASIC and high density FPGA user requiring high performance verification software. The product offers extensive scripting support and direct interfaces to our Hardware Embedded Simulation technology that when combined with Riviera yields a 10x+ increase in simulation performance on designs greater then 500,000 gates.” stated Michael O’Brien, Product Marketing Manager at Aldec.
Availability
Riviera is currently available and includes an HDL Editor, Debugger, Waveform Viewer and choice of a VHDL, Verilog or mixed VHDL, Verilog and EDIF simulation. The product currently supports Linux Red Hatâ 6.x. The first year of maintenance is included and all licenses are transferable to NT and UNIX once supported. To receive your FREE evaluation copy of Riviera, visit Aldec at www.aldec.com and register online to obtain an evaluation.
About Aldec
Aldec has offered PC-based design entry and simulation solutions to FPGA designers for more than 15 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY) Aldec, Inc., headquartered in Henderson, Nevada, produces a universal suite of Windows based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the Windows-based EDA market as the fastest growing privately held EDA supplier in the world. Additional information about Aldec is available at http://www.aldec.com.
Active-HDL, HES and Incremental Prototyping are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners
|
|
CaféTalk
